1. Field of the Invention
The present invention relates to integrated circuit structures and, in particular, to metal interconnect contact structures for use in integrated circuits and processes for their manufacture.
2. Description of the Related Art
Typical integrated circuits (ICs) include metal interconnect structures that serve a variety of purposes, such as carrying electrical signals between individual device elements in the IC, supplying power, and providing a connection to ground and to external apparatus.
FIG. 1 illustrates a basic metal interconnect structure 10 disposed above a semiconductor substrate 12. Metal interconnect structure 10 includes patterned metal layer 14, interconnect dielectric material layer 16, and contacts 18, 20 and 22. Semiconductor substrate 12 has a conventional MOS transistor formed on its surface that includes source region 24, drain region 26, gate sidewall spacers 28 and 30, polysilicon gate layer 32 and gate oxide layer 34. The contacts 18, 20 and 22 of metal interconnect structure 10 provide an electrical connection between the patterned metal layer 14 and various parts of the MOS transistor: the source region 24, polysilicon gate layer 32 and drain region 26, respectively.
FIG. 2 illustrates a conventional and more elaborate design of a metal interconnect contact 40, which includes a first metallic layer 42, a second metallic layer 44 and a center plug (i.e. core) 46. See U.S. Pat. No. 5,514,622 to Bornstein et al., which is hereby fully incorporated by reference, for a further description of metal interconnect structures in general. The first metallic layer 42 of the metal interconnect contact 40 is conventionally a titanium adhesion layer, while the second metallic layer 44 is a titanium-nitride (TiN) layer. The center plug 46 is typically formed of tungsten (W). Standard tungsten plug deposition processes employ WF.sub.6. The presence of a TiN layer in the metal interconnect contact acts as a barrier layer to prevent WF.sub.6 from reacting with silicon from the source region, drain region or the polysilicon gate layer during the tungsten plug deposition process. The use of a Ti layer in the metal interconnect contact is designed to improve the adhesion of the TiN layer to the Ti layer, as well as the adhesion of the W plug to the TiN layer. The presence of the Ti layer in the metal interconnect contact also improves the contact resistance between the patterned metal layer and the various parts of the MOS transistor, namely the source region, polysilicon gate layer and drain region.
The Ti and TiN layers employed in metal interconnect contacts are often subjected to a thermal annealing process to further improve contact resistance. This is normally done using rapid thermal annealing (RTA) equipment at temperatures in the range of 600.degree. C. to 700.degree. C. The data in Table 1 below show the effect of such an RTA process, namely that contact resistance is inversely proportional to the temperature of the RTA process. Therefore, as the temperature increases, the contact resistance advantageously decreases.
TABLE 1 ______________________________________ Average Patterned Metal to RTA Temperature Polysilicon Contact Resistance ______________________________________ No RTA 3.9 ohms/square 600.degree. C. 2.9 ohms/square 650.degree. C. 2.6 ohms/square 700.degree. C. 2.3 ohms/square ______________________________________
An increase in the temperature of the RTA process, however, also increases the junction leakage of the P+ source and/or drain, which is detrimental to integrated circuit device characteristics. This effect of the RTA process temperature on the junction leakage is indicated by the data in Table 2 below.
TABLE 2 ______________________________________ Average P+ Junction Leakage RTA Temperature log (amps) ______________________________________ No RTA -10.3 600.degree. C. -9.9 650.degree. C. -9.3 700.degree. C. -9.0 ______________________________________
Still needed in the art is a metal interconnect contact, and process for its manufacture, that provides for both low contact resistance and low junction leakage. In addition, the process for its manufacture should be compatible with standard integrated circuit manufacturing techniques.